This invention relates generally to computer systems and more particularly to testing of busses of computer systems.
As it is known in the art, a computer system includes inter alia a central processing unit for processing an instruction set, a memory to store instructions, a bus to interconnect the memory to the CPU and an Input/Output (I/O) interface to couple I/O buses and I/O devices to the CPU. In many computer systems a memory device controller often includes logic to perform Direct Memory Access (DMA) which is used by the CPU to transfer large blocks of information amongst the memory, the central processor and I/O devices. The Input/Output (I/O) device, coupled to the system bus provides an interface between external devices and the memory and central processing unit. The external devices are generally coupled to the I/O device by an I/O bus.
In many computer system applications such as in computer networks, the I/O busses are high speed transmission systems which allow for a transfer of large blocks of data between the external device and memory. For example, an external device may be a console device, a graphics device, a printer, a disk, or a network interface.
Often the I/O bus, particularly an I/O bus used in network applications, is capable of transferring data at a much higher bandwidth than the processing system. This is desirable to prevent the processor from wasting processing time while it waits for data to be transmitted over the I/O bus. Moreover, in networked applications often many computer systems are interconnected to a common I/O bus and therefore the bus needs sufficient bandwidth to adequately service all of the systems on the bus.
One type of bus protocol has the external device and the I/O device communicating using an asynchronous, master/slave interface protocol. According to the master/slave protocol, one device (the master) sends out a request for data over the bus, and awaits an acknowledgement from the external device that the request has been received. The slave device acknowledges the receipt of the request, and executes the instruction from the master device. For example, if the master device requested a write, it would send out the write request, and not proceed executing a subsequent request until it receives the acknowledgement from the slave device. In this manner, the master/slave protocol thus ensures that I/O requests are not dropped without execution by the slave device.
As with any other computer system device testing of the device is often performed to insure that the device is operating properly. Testing is also performed to insure that the design is free of flaws.
Due to the high bandwidth of the I/O bus, it is often difficult during the manufacturing of computer systems to ensure that the I/O bus, and its associated interfaces are operating as expected according to the bus protocol. It is often difficult to discover errors in the I/O bus interface design since many of the design flaws will not arise until the bus is operating at or near its maximum capacity, that is using the full bandwidth of the I/O bus.
Thus, it would be desirable to thoroughly test the I/O bus at a bandwidth which approaches the maximum bandwidth of the I/O bus levels, before the I/O bus interfaces are actually integrated and running in the computer system. Testing the I/O bus at maximum bandwidth is further complicated due to the fact that parity generation is generally provided in the I/O data path, which increases the propagation delay of I/O data before it reaches the I/O bus. The time required for parity generation directly subtracts from the speed at which data can be provided to the bus.